Digital-to-analog converters are widely used for converting digital signals to corresponding analog signals for many electronic circuits. For example, a high resolution, high speed digital-to-analog converter (DAC) may find applications in cellular base stations, wireless communications, direct digital frequency synthesis, signal reconstruction, test equipment, high resolution imaging systems and arbitrary waveform generators, for example.
The requirements of the telecommunication applications demand 10–16-bit D/A-converters that can operate at sampling frequencies of hundreds of megahertz. For the high-speed operation, the current-steering topology is the mostly used choice. Though there are methods to design a current-steering DAC to fulfil a 14-bit DC-linearity with some yield, the high frequency behaviour becomes unacceptable. In commercial DAC's, where the dynamic behaviour has a higher priority, the high yield DC-linearity is in the order of 10–12-bit.
The high-resolution (>10 bit) current-steering D/A-converters are typically divided into two or more different subsets, so that each of the subsets makes a conversion of some of the input bits from digital signal into an analog current. An example of such a topology is shown in FIG. 1. The MSB-subset is the most critical because it converts the most significant bits, and therefore most of the output signal.
In a segmented current steering DAC the MSB-block or subset is a matrix of unweighted current sources that are controlled by thermometer decoded input bits. This means that for example 6 MSB's are thermometer decoded into 63 control signals which control the 63 differential current switches. Because one of the 64 signal levels that 6-bit binary word (26) can point is 0, only 63 signals are needed. The LSB-block has typically binary-weighted current sources that are controlled by the LSB's without any decoding. In addition to that, there can be a middle bit conversion that can be both binary-weighted or unweighted.
The use of some calibration method is a good way of designing a high-resolution DAC for high AC-linearity performance. In the calibration case the design can focus on getting a good high frequency behaviour and leaving the calibration to handle the DC-linearity requirements.
The DC-linearity of the current steering DAC is mainly affected by the matching of the current source transistors in the MSB subset. The random mismatch of a current source can be calculated using the following equation (1):
                                                                        (                                                      σ                    Id                                    Id                                )                            2                        =                                          σ                k                2                            +                                                                    4                    *                                          σ                                              Δ                        ⁢                                                                                                  ⁢                        Vth                                            2                                                                                                  (                                                                        V                          gs                                                -                                                  V                          t0                                                                    )                                        2                                                  .                                              ⁢                                          ,                                          ⁢          where                ⁢                                  ⁢                              σ            k                    =                                                    A                                                      W                    *                    L                                                              ⁢                                                          ⁢              and              ⁢                                                          ⁢                              σ                                  Δ                  ⁢                                                                          ⁢                  Vth                                                      =                                                            A                  vth                                                                      W                    *                    L                                                              .                                                          (        1        )            
A and Avth are the process dependent variables. W and L are the width and the length of the current source transistor, respectively, and Vgs is the gate-source voltage of the transistor.
As an example a relative current distribution in percentages of current sources with σ=0.225% mismatch is shown in FIG. 2
In addition to the random mismatch there is also some systematic errors that are mainly caused by process related gradients and voltage drops in the supply lines. The cumulation of the systematic errors can be compensated with careful layout design. Also some switching order randomising is used.
The switching order of the current source array is typically selected so that the cumulating of the systematic errors are evenly spread over the full ramp signal. One of the most common methods is symmetrical switching. However, the switching order randomising affects only the systematic error cumulating. Also the shape of the cumulating error affects the dynamic performance. Especially if the INL curve is heavily bowed, the DC-non-linearity can increase the distortion. On the other hand, the large INL error increases the quantization noise.
In FIGS. 3a and 3b are DNL and INL curves of the unweighted array referred to 14-bit resolution. The 63 current sources are ideal added with a random error of σId=0.225%. Each of the current sources is described with the following equation. The result is from 1000 Matlab simulations.
                                          I            MSBi                    =                                    I              MSBi0                        *                          (                              1                +                                                      X                    rand                                    *                                                            σ                      Id                                                              I                      d                                                                                  )                                      ,                            (        2        )            where
Xrand is a normally distributed random number. IMSB0 is the ideal current and σId/Id is the standard deviation of the error. FIG. 4 and FIG. 5 show the relative distribution of the DNL and INL errors. As shown in FIG. 5, a typical INL is nearly 12-bit and only 11-bits is achievable with high yield.
The mismatch of the current sources determines the DC-linearity behaviour of the whole D/A-converter. The target is to have both the DNL and the INL values less than 0.5 LSB. The differential non-linearity (DNL) describes how large the step deviation from 1 LSB is. The integral non-linearity (INL) shows the cumulating sum of the errors. Therefore for the sufficient DC-linearity, the mismatch should be small enough so as not to deviate the currents too much from the nominal. Due to the Gaussian distribution nature of the random mismatch, the design margins must be relatively large to guarantee a high yield.
However, if the DAC is designed to fill the DC-linearity specification, the high frequency behaviour is typically bad, because this leads to non-optimal design for high frequency signals.
In prior-art solutions, a non-calibrated high-resolution DAC has typically low or intermediate high frequency behaviour, due to the optimisation for full DC-linearity. Therefore for high-resolution and high-frequency performance, some calibration is highly desired.
A pseudo calibration method called dynamic element matching is a common method, especially in D/A-converters inside sigma-delta type of data converters. The method spreads the linearity errors to the noise floor by continuously changing the order of the switching pattern.
The actual calibration methods have two main bases, trimming the actual current sources, or having an extra low precision DAC to generate a correction term to the output. These methods need typically a continuous calibration due to the changing conditions. For example temperature or biasing conditions can vary.
The drawbacks of these prior-art solutions are as follows. The layout techniques that focus on distribution of the systematic errors cannot affect the errors that are generated by the random mismatch of the transistors. The use of parallel arrays can average these random errors, but the circuit complexity still decreases the high frequency performance. Also, since the random mismatch is a function of the transistor area and overdrive voltage, designing a high resolution DAC consumes both area and power. The most important issue, however, is that the designing for full DC-linearity decreases the high-frequency behaviour. Therefore, these DAC's are typically not suitable for high-speed operation.
The dynamic element matching method spreads the DC-linearity errors into the noise floor, and therefore the errors still exists even though the distortion is low. The SNDR (Signal-to-noise-and-distortion) value is still the same in the frequency band of fsample/2 with or without the dynamic matching method, and therefore the actual effective number of bits does not increase at all.
The use of current source that can be trimmed increases the complexity of the analog parts in the DAC, and therefore the DAC is not easy to be optimised for high frequency performance. The prior art calibration methods are sensitive to the changes in the biasing or ambient temperature.
If the additional DAC or current sources are used in the calibration, the complexity of the analog part is further increased. These methods also lead to problems in high-frequency operation, since the penalty is an imbalance in the main DAC.
U.S. Pat. No. 6,118,398 describes a digital-to-analog converter (DAC) which includes a plurality of current sources on a substrate operable in a predetermined sequence of use for generating an output current based upon a digital input, and a connection network for establishing the predetermined sequence of use for the current sources based upon the actual current values and for increasing the performance of the DAC. Said connection network can be used to reduce integral non-linearity error of the DAC. The connection network may be provided by a plurality of fusible links selectively connected to set the predetermined sequence of use. The connection network is, however, connected after the digital part of the whole converter and is thus located on the analog side. This makes the design of the analog more complex and remarkably affects the high frequency linearity of the analog side. The plurality of the current sources has actual values that can be sorted from lowest to highest, and each actual current value will define an error value with both a magnitude and polarity relative to the desired value. One embodiment for sorting the order of use of the current sources is based upon the error values.
The purpose or target of the present invention is to decrease the high variation in the INL curves, so that the cumulating of the errors does not generate highly bowed linearity curves. On the other hand, moving the maximum deviations near the zero- and full-scale codes, the limiting of the signal swing can always decrease the effect of the DC errors from the signal. When the cumulating of the errors is reduced, the calibrated INL is always less than without the calibration.
Further, the object of the present invention is to provide a digital-to-analog converter design in which the improvement of the DC-linearity is achieved with less effects on the AC-linearity.